Ansys medini analyze supports key safety analysis methods at various levels of a chip, ranging from IP Design of integrated components, up to SoCs and electronic boards.
Functional Safety Analysis for Semiconductors
Ansys medini analyze supports best-practice workflows that graphically link specific areas of the semiconductor design to key functions within the electronics architecture. This allows engineers to analyze and address potential failure modes as they verify the functional safety of semiconductor components. Engineers can efficiently and consistently execute the safety-related activities such as the FMEDA, required by safety standards like ISO 26262: 2018 part 11.
- Failure Rate Prediction
- Map Chip Design to Functions
- Failure Mode Effect and Diagnostic Analysis
- Digital and Analog Chip Analysis
Streamline and automate functional safety analysis across the entire electronics architecture — including down to the chip level. Any inconsistencies in the functional safety analysis are eliminated, and confirmation reviews and assessments are accelerated.
- Failure Rate Distribution by Die Area
- Requirement Traceability
- IP Design Import
- Determine and Analyze Potential Failure Modes
- Safety Mechanism Design
- Map Blocks of the Semiconductor Design to System Functions
- Transient Failure Analysis
- Diagnostic Coverage Analysis