Webinar: Variability-aware and SPICE-accurate Timing Closure
- 18th April 2018
3:00 pm - 4:00 pm
Many sources of on-chip variation are conspiring to kill your project. Learn how the ANSYS FX platform, with its unique variation-aware technology, can save you from gross inaccuracies in modeling variation. Important topics include SPICE-accurate process variation, especially at low voltage; SPICE-accurate voltage variation including clock jitter due to IR drop; and a methodology shift in modeling chip-level aging that is easier, faster and more accurate than current approaches.
Brett Yokom is an experienced EDA professional with 11+ years of experience. He joined ANSYS in September of 2013 and is currently Lead Technical Project Manager for FX technologies.
Brett started his career at IBM, working on both front-end and back-end design for custom clocks and timing closure. As a part of ANSYS, Brett has been guiding customers with timing variation adoptions of FX technologies including Liberty Variance Format (LVF), Constraint Uncertainty, and PathFX.
Webinar starts at 15:00
Who Should Attend?
Designers, engineers, managers and directors seeking to optimise their design & development processes.
Registration / Further Information
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Please note that this event is free to attend but registration is essential.
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