ANSYS Webinar: Leveraging Chip Power Models for System-Level EMC Simulation of Automotive ICs

The design of integrated circuits (ICs) for electromagnetic compatibility (EMC) is a fundamental requirement for the security and safety of automotive electronics systems. These must be tested for noise emission, electromagnetic interference (EMI) and for electromagnetic susceptibility (EMS) with intentional radio frequency (RF) disturbance. To achieve safety goals, chip power model (CPM) simulation is extended to evaluate the creation of noise from ICs and to capture the response of ICs to RF disturbance. This is done by leveraging the ANSYS chip ESD compact model (CECM) that captures the snapback current-voltage transfer characteristics of the ESD protection devices, silicon substrate coupling around the devices and also the chip-package-printed circuit board (PCB) interaction. The measurements and simulation are demonstrated with silicon test chips.

In this webinar,  Karthik Srinivasan, senior product manager from ANSYS and Dr. Makoto Nagata from Kobe University, Japan, will demonstrate how integrated circuit (IC), package and board designers can leverage ANSYS chip models in system-level simulations to meet the strict EMC requirements.

Webinar starts at 17:00 GMT

Who Should Attend?

Designers, engineers, managers and directors seeking to optimise their design & development processes.

Registration / Further Information

Simply choose one of the following options to receive further information or to register.

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Please note that this event is free to attend but registration is essential.

In this webinar, Karthik Srinivasan, senior product manager from ANSYS and Dr. Makoto Nagata from Kobe University, Japan, will demonstrate how integrated circuit (IC), package and board designers can leverage ANSYS chip models in system-level simulations to meet the strict EMC requirements.